Part 2AMENDMENTS TO THE EXPORT CONTROL ORDER 2008
Amendments to Schedule 3 (UK Controlled Dual-Use Goods, Software and Technology)
regulation 5 5. In Schedule 3—
regulation 5 a (a)for entry PL9013.a.3.a. to entry PL9013.a.3.f., at the end of each entry for “,” substitute “;”;
regulation 5 b (b)for entry PL9013.a.4., including the Note, Technical Notes and the N.B., substitute—
| 4. | Integrated circuits having one or more digital processing units having a ‘Total Processing Performance’ (‘TPP’) of 6,000 or more. | |||
| N.B.: | For “digital computers” and “electronic assemblies” containing integrated circuits specified in PL9013.a.4., see PL9014.a.2.. | |||
| Technical Notes: | ||||
| For the purposes of PL9013.a.4.: | ||||
| 1. | ‘Total processing performance’ (‘TPP’) is 2 x ‘MacTOPS’ x ‘bit length of the operation’, aggregated over all processing units on the integrated circuit. | |||
| a. | ‘MacTOPS’ is the theoretical peak number of Tera (1012) operations per second for multiply-accumulate computation, D=AxB+C). | |||
| b. | The 2 in the ‘TPP’ formula is based on the industry convention of counting one multiply-accumulate computation, D=AxB+C, as 2 operations for the purpose of datasheets. Therefore, 2 x MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet. | |||
| c. | ‘Bit length of the operation’ for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation. | |||
| d. | Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. ‘TPP’ = TPP1 + TPP2 +… + TPPn (where n is the number of processing units on the integrated circuit). | |||
| 2. | The rate of ‘MacTOPS’ is to be calculated at its maximum value theoretically possible. The rate of ‘MacTOPS’ is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the ‘TPP’ threshold of 6,000 can be met with 750 tera integer operations (or 2 x 375 ‘MacTOPS’) at 8 bits or 300 tera FLOPS (or 2 x 150 ‘MacTOPS’) at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different ‘TPP’ values, the highest ‘TPP’ value should be evaluated again parameters in PL9013.a.4.. | |||
| 3. | For integrated circuits, specified in PL9013.a.4., that provide processing of both sparse and dense matrices, the ‘TPP’ values are the values for processing of dense matrices (e.g., without sparsity).; | |||
regulation 5 c (c)in entry PL9013.a.5.a and entry PL9013.a.5.b., at the end, for “,” substitute “;”;
regulation 5 d (d)in entry PL9014.a.2., for the Note substitute—
| “Note: | PL9014.a.2. includes “digital computers” and hybrid computers.”. | |||